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LRS1331
Data Sheet
FEATURES
* Flash Memory and SRAM * Stacked Die Chip Scale Package * 72-ball 8 mm x 11 mm CSP plastic package * Power supply: 2.7 V to 3.6 V * Operating temperature: -25C to +85C * Flash Memory - Access time (MAX.): 90 ns - Operating current (MAX.) (The current for F-VCC pin and F-VCCW pin): - Read: 25 mA (tCYCLE = 200 ns) - Word write: 57 mA - Block erase: 42 mA - Standby current (the current for F-VCC pin): 15 A (MAX. F-RP GND 0.2 V) - Optimized array blocking architecture - Two 4K-word boot blocks - Six 4K-word parameter blocks
Stacked Chip 16M Flash Memory and 4M SRAM
- Thirty-one 32K-word main blocks - Bottom boot location - Extended cycling capability - 100,000 block erase cycles - Enhanced automated suspend options - Word write suspend to read - Block erase suspend to word write - Block erase suspend to read * SRAM - Access time (MAX.): 85 ns - Operating current: 45 mA (MAX.) - Standby current: 15 A (MAX.) - Data retention current: 2 A (MAX.)
DESCRIPTION
The LRS1331 is a combination memory organized as 1,048,576 x 16-bit flash memory and 262,144 x 16-bit static RAM in one package.
PIN CONFIGURATION
72-BALL FBGA INDEX TOP VIEW
1 A B C D E F G H NC NC
2 NC
3 NC A16
4 A11 A8
5 A15 A10 T1
T2
6 A14 A9
7 A13
8 A12
9 F-GND
10 NC
DQ7 DQ5
11 NC
12 NC
DQ15 S-WE DQ14 DQ6 DQ4
F-WE F-RY/ BY
S-A17 DQ13 T4
GND F-RP F-WP
DQ12 S-CE2 S-VCC F-VCC T3 DQ9 DQ10 DQ2 DQ8 DQ0 DQ3 DQ1
F-VPP F-A19 DQ11 NC
S-LB S-UB S-OE F-A18 NC NC F-A17 A5 A7 A4
A6 A0
A3
A2
A1
S-CE1 NC NC NC
F-CE F-GND F-OE
NOTE: All F-GND and S-GND pins are connected on the board. Two NC pins at the corner are connected.
LRS1331-1
Figure 1. LRS1331 Pin Configuration
Data Sheet
1
LRS1331
Stacked Chip (16M Flash & 4M SRAM)
F-VCC F-VPP F-GND F-A17 to F-A19 A0 to A16 F-CE F-OE F-WE F-RP F-WP DQ0 to DQ15 S-A17 S-CE1 S-CE2 S-OE S-WE S-UB S-LB 4M (x16) BIT SRAM 16M (x16) BIT FLASH MEMORY F-RY/BY
S-VCC
S-GND
LRS1331-2
Figure 2. LRS1331 Block Diagram
2
Data Sheet
Stacked Chip (16M Flash & 4M SRAM)
LRS1331
Table 1. Pin Descriptions PIN A0 to A16 F-A17 to F-A19 S-A17 F-CE S-CE1, S-CE2 F-WE S-WE F-OE S-OE S-LB S-UB F-RP DESCRIPTION Address Inputs (Common) Address Inputs (Flash) Address Input (SRAM) Chip Enable Input (Flash) Chip Enable Inputs (SRAM) Write Enable Input (Flash) Write Enable Input (SRAM) Output Enable Input (Flash) Output Enable Input (SRAM) SRAM Byte Enable Input (DQ0 to DQ7) SRAM Byte Enable Input (DQ8 to DQ15) Deep Power Down Input (Flash) Block erase and Word Write: VIH Read: VIH Deep Power Down: VIL Write Protect Input (Flash) Two Boot Blocks Locked: VIL Ready/Busy Output(Flash) During an Erase or Write operation: VOL Block Erase and Word Write Suspend: HIGH-Z Deep Power Down: VOH Data Input and Outputs (Common) Power Supply (Flash) Power Supply (SRAM) Write, Erase Power Supply (Flash) Block Erase and Word Write: F-VPP = VPPLK All Blocks Locked: F-VPP < VPPLK Ground (Flash) Ground (SRAM) No Connection Test Pins (Should be Open) TYPE Input Input Input Input Input Input Input Input Input Input Input Input
F-WP
Input
F-RY/BY DQ0 to DQ15 F-VCC S-VCC F-VPP F-GND S-GND NC T1 to T5
Output Input/Output Power Power Power Power Power -- --
Data Sheet
3
LRS1331 Table 2. Truth Table1
FLASH Read Output Disable Write SRAM Standby Standby Standby Read Standby Output Disable Write Read Reset Output Disable Write Standby Reset Standby Standby F-CE L L L H H H H X X X X H X F-RP H H H H H H H L L L L H L F-OE L H H X X X X X X X X X X F-WE H H L X X X X X X X X X X L L L L L L L L H H H H H H H H See Note 4 S-CE1 S-CE2 S-OE X X X L H X L L H X L X X
Stacked Chip (16M Flash & 4M SRAM)
S-WE X X X H H X L H H X L X X
S-LB
S-UB
DQ0 DQ7
DQ8 DQ15
NOTES 2, 3 3 2, 3, 5, 6
DOUT See Note 4 HIGH-Z DIN See Note 7 X H X H HIGH-Z HIGH-Z
See Note 7 X H X H HIGH-Z HIGH-Z
See Note 7 See Note 4 HIGH-Z HIGH-Z 3 3
See Note 4
NOTES: 1. L = VIL, H = VIH, X = H or L. Refer to DC Characteristics. 2. Refer to the `Flash Memory Command Definition' section for valid address input and DIN during a write operation. 3. F-WP set to VIL or VIH. 4. SRAM standby data. See Table 2a. Table 2a. MODE PINS S-CE1 H Standby (SRAM) X X S-CE2 X L X S-LB X X H S-UB X X H
5. Command writes involving block erase or word write are reliably executed when VCCWH (2.7 V to 3.6 V) and F-VCC = 2.7 V to 3.6 V. Block erase or word write with F-VCCW < VCCWH (MIN.) produce spurious results and should not be attempted. 6. Never hold F-OE LOW and F-WE LOW at the same timing. 7. S-LB, S-UB Control Mode. See Table 2b. Table 2b. MODE (SRAM) PINS S-LB L Read/Write L H S-UB L H L DQ0 - DQ7 DOUT/DIN DOUT/DIN HIGH-Z DQ8 - DQ15 DOUT/DIN HIGH-Z DOUT/DIN
4
Data Sheet
Stacked Chip (16M Flash & 4M SRAM) Table 3. Command Definition for Flash Memory1
COMMAND Read Array/Reset Read Identifier Codes Read Status Register Clear Status Register Block Erase Full Chip Erase Word Write Block Erase and Word Write Suspend Block Erase and Write Resume Set Block Lock-Bits Clear Block Lock-Bits Set Permanent Lock-Bits BUS CYCLES REQUIRED 1 2 2 1 2 2 2 1 1 2 2 2 FIRST BUS CYCLE OPERATION2 Write Write Write Write Write Write Write Write Write Write Write Write ADDRESS3 XA XA XA XA BA XA WA XA XA BA XA XA DATA3 FFH 90H 70H 50H 20H 30H 40H or 10H B0H D0H 60H 60H 60H Write Write Write BA XA XA 01H D0H F1H Write Write Write BA XA WA D0H D0H WD Read Read IA XA ID SRD SECOND BUS CYCLE OPERATION2 ADDRESS3
LRS1331
DATA3
NOTES
4
5
5 5 5 6 6, 7
NOTES: 1. Commands other than those shown in table are reserved by SHARP for future device implementations and should not be used. 2. BUS operations are defined in Table 2. 3. XA = Any valid address within the device; IA = Identifier code address; BA = Address within the block being erased; WA = Address of memory location to be written; SRD = Data read from status register; WD = Data to be written at location WA. Data is latched on the rising edge of F-WE or F-CE (whichever goes HIGH first); ID = Data read from identifier codes. 4. See Table 4 for Identifier Codes. 5. See Table 5 for Write Protection Alternatives. 6. If the permanent lock-bit is set, Set Block Lock-Bit and Clear Block Lock-Bits commands cannot be done. 7. The clear block lock-bits operation simultaneously clears all block lock-bits.
Table 4. Identifier Codes CODES Manufacture Code Device Code Block Lock Configuration Permanent Lock Configuration Block is Unlocked Block is Locked Device is Unlocked Device is Locked ADDRESS (A0 - A19) 00000H 00001H BA + 2 BA + 2 00003H 00003H DATA (DQ0 - DQ7)1 B0H E9H DQ0 = 0 DQ0 = 1 DQ0 = 0 DQ0 = 1 2 2 NOTES
NOTES: 1. DQ8 - DQ15 outputs 00H in word mode. DQ1 - DQ7 are reserved for future use. 2. BA selects the specific block lock configuration code to be read. See Figure 3 for the device identifier code memory map.
Data Sheet
5
LRS1331
Stacked Chip (16M Flash & 4M SRAM)
Table 5. Write Protection Alternatives
OPERATION F-VCCW F-RP PERMANENT BLOCK LOCK-BIT LOCK-BIT F-WP EFFECT All blocks locked All blocks locked Two boot blocks locked Block Erase and Word Write enabled Block Erase and Word Write disabled Block Erase and Word Write disabled All blocks locked All blocks locked All unlocked blocks are erased. Two boot blocks and locked blocks are not erased All unlocked blocks are erased. Locked blocks are not erased Set block lock-bit disabled Set block lock-bit disabled Set block lock-bit enabled Set block lock-bit disabled Clear block lock-bits disabled Clear block lock-bits disabled Clear block lock-bits enabled Clear block lock-bits disabled Set permanent lock-bit disabled Set permanent lock-bit disabled Set permanent lock-bit enabled
VCCWLK
Block Erase or Word Write
X VIL
X X
X X 0
X X VIL VIH VIL VIH X X VIL
> VCCWLK
VIH
X 1
VCCWLK
Full Chip Erase
X VIL
X X X X X 0 1 X X 0 1 X X X
X X X
> VCCWLK
VIH X VIL
VIH VCCWLK
Set Block Lock-Bit
X X X X X X X X X X X
X X X X X X X X X X X
> VCCWLK VCCWLK
VIH X VIL
Clear Block Lock-Bit
> VCCWLK VCCWLK
VIH X VIL VIH
Set Permanent Lock-Bit
> VCCWLK
6
Data Sheet
Stacked Chip (16M Flash & 4M SRAM)
LRS1331
Table 6. Status Register Definition
WSMS 7 BESS 6 ECBLBS 5 WBWSLBS 4 VCCWS 3 WBWSS 2 DPS 1 R 0
SR.7 = Write State Machine Status (WSMS) 1 = Ready 0 = Busy SR.6 = Erase Suspend Status (BESS) 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = Erase and Clear Block Lock-Bits Status (ECBLBS) 1 = Error in Block Erase, Bank Erase or Clear Block Lock-Bits 0 = Successful Block Erase, Bank Erase or Clear Block Lock-Bits SR.4 = Word/Byte Write and Set Lock-Bit Status (WBWSLBS) 1 = Error in Word/Byte Write or Set Block/Permanent Lock-Bit 0 = Successful Word/Byte Write or Set Block/Permanent Lock-Bit SR.3 = VCCW Status (VCCWS) 1 = VCCW LOW Detect, Operation Abort 0 = VCCW Okay SR.2 = Word/Byte Write Suspend Status (WBWSS) 1 = Word/Byte Write Suspended 0 = Word/Byte Write in Progress/Completed SR.1 = Device Protect Status (DPS) 1 = Block Lock-Bits, Permanent Lock-Bits and/or F-WP Lock Detected, Operation Abort 0 = Unlock SR.0 = Reserved for future enhancements (R)
NOTES: 1. Check SR.7 to determine block erase, bank erase, word/byte write or lock-bit configuration completion. SR.6 - SR.0 are invalid while SR.7 = 0. 2. If both SR.5 and SR.4 are `1's after a block erase, bank erase or lock-bit configuration attempt, an improper command sequence was entered. 3. SR.3 does not provide a continuous indication of F-VCCW level. The WSM interrogates and indicates the F-VCCW level only after block erase, bank erase, word/byte write or lock-bit configuration command sequences. SR.3 is not guaranteed to report accurate feedback only when F-VCCW F-VCCWH. 4. SR.1 does not provide a continuous indication of permanent and block lock-bit and F-WP values. The WSM interrogates the permanent lock-bit, block lock-bit and F-WP only after block erase, bank erase, word/byte write or lock-bit configuration command sequences. It informs the system, depending on the attempted operation, if the block lock-bit is set, permanent lock-bit is set and/ or F-WP is VIL. Reading the block lock and permanent lock configruation codes after writing the Read Identifier codes command indicates permanent and block lock-bit status.. 5. SR.0 is reserved for future use and should be masked out when polling the status register.
Data Sheet
7
LRS1331
Stacked Chip (16M Flash & 4M SRAM)
MEMORY MAP
[A0 - A19] FFFFF F8000 F7FFF F0000 EFFFF E8000 E7FFF E0000 DFFFF D8000 D7FFF D0000 CFFFF C8000 C7FFF C0000 BFFFF B8000 B7FFF B0000 AFFFF A8000 A7FFF A0000 9FFFF 98000 97FFF 90000 8FFFF 88000 87FFF 80000 7FFFF 78000 77FFF 70000 6FFFF 68000 67FFF 60000 5FFFF 58000 57FFF 50000 4FFFF 48000 47FFF 40000 3FFFF 38000 37FFF 30000 2FFFF 28000 27FFF 20000 1FFFF 18000 17FFF 10000 0FFFF 08000 07FFF 07000 06FFF 06000 05FFF 05000 04FFF 04000 03FFF 03000 02FFF 02000 01FFF 01000 00FFF 00000
32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
4K-WORD PARAMETER BOOT BLOCK 5 4K-WORD PARAMETER BOOT BLOCK 4 4K-WORD PARAMETER BOOT BLOCK 3 4K-WORD PARAMETER BOOT BLOCK 2 4K-WORD PARAMETER BOOT BLOCK 1 4K-WORD PARAMETER BOOT BLOCK 0 4K-WORD BOOT BLOCK 4K-WORD BOOT BLOCK BOTTOM BOOT
LRS1331-3
1 0
Figure 3. Memory Map for Flash Memory
8
Data Sheet
Stacked Chip (16M Flash & 4M SRAM)
LRS1331
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply voltage Input voltage Operating temperature Storage temperature F-VCCW voltage SYMBOL VCC VIN TOPR TSTG F-VCCW RATINGS -0.2 to +4.6 -0.2 to VCC +0.3 -25 to +85 -65 to +125 -0.5 to +4.6 UNIT V V C C V 1, 3 NOTES 1 1, 2, 3
NOTES: 1. The maximum applicable voltage on any pins with respect to GND. 2. Except F-VCC, F-VCCW. 3. -2.0 V undershoot is allowed when the pulse width is less than 20 ns.
RECOMMENDED DC OPERATING CONDITIONS
TA = -25C to +85C PARAMETER Supply voltage Input voltage SYMBOL VCC VIH VIL MIN. 2.7 2.2 -0.3 TYP. 3.0 MAX. 3.6 VCC + 0.2 0.6 UNIT V V V 1 2 NOTES
NOTES: 1. VCC is the lower one of S-VCC and F-VCC. 2. -2.0 V undershoot is allowed when the pulse width is less than 20 ns.
PIN CAPACITANCE
TA = 25C, f = 1 MHz PARAMETER Input capacitance* I/O capacitance* SYMBOL CIN CI/O CONDITION VIN = 0 V VI/O = 0 V MIN. TYP. MAX. 20 22 UNIT pF pF
NOTE: *Sampled by not 100% tested.
Data Sheet
9
LRS1331
Stacked Chip (16M Flash & 4M SRAM)
DC CHARACTERISTICS
TA = -25C to + 85C, VCC = 2.7 V to 3.6 V
PARAMETER Input leakage current Output leakage current SYMBOL ILI ILO CONDITION VIN = VCC or GND VOUT = VCC or GND F-CE = F-RP = F-VCC 0.2 V F-WP = F-VCC 0.2 V or F-GND 0.2 V F-CE = F-RP = VIH, F-WP = VIH or VIL Auto Power-Save Current Reset/Power-Down Current F-VCC Read Current ICCR ICCAS ICCD F-CE = GND 0.2 V F-RP = F-GND 0.2 V, IOUT (F-RY/BY) = 0 mA CMOS input, F-CE = F-GND, f = 5 MHz, IOUT = 0 mA TTL input, F-CE = F-GND, f = 5 MHz, IOUT = 0 mA F-VCCW = VCCWH F-VCCW = VCCWH F-CE = VIH F-VPP F-VCC F-VPP > F-VCC F-CE = GND 0.2 V F-RP = F-GND 0.2 V F-VCCW = VCCWH F-VCCW = VCCWH F-VCCW = VCCWH S-CE1, S-CE2 S-VCC - 0.2 V or S-CE2 0.2 V S-CE1 = VIH or S-CE2 = VIL S-CE1 = VIL, S-CE2 = VIH, VIN = VIL or VIH, tCYCLE = MIN., II/O = 0 mA S-CE1 = 0.2 V, S-CE2 = S-VCC - 0.2 V, VIN = S-VCC - 0.2 V, or 0.2 V tCYCLE = 1 s, II/O = 0 mA -0.3 2.2 IOL = 0.5 mA IOH = -0.5 mA 2.2 1.5 2.7 2.0 3.6 5 4 1 2 10 0.1 0.1 12 8 10 MIN. -1.5 -1.5 2 0.2 2 2 15 TYP.1 MAX. +1.5 +1.5 15 2 15 15 25 30 17 17 6 15 200 5 5 40 25 200 15 3 45 UNIT A A A mA A A mA mA mA mA mA A A A A mA mA A A mA mA 2, 3 2 2 2, 3 2 2 2 2 NOTES
Standby Current
ICCS
Word Write or Set Lock-Bit Current Block Erase, Full Chip Erase or Clear Block Lock-BIts Current Word Write Block Erase Suspend Current Standby or Read Current Auto Power-Save Current Reset/Power-Down Current F-VCCW Word Write or Set Lock-Bit Current Block Erase, Full Chip Erase or Clear Block Lock-Bits Current Word Write or Block Erase Suspend Current Standby Current
ICCW ICCE ICCWS ICCES ICCWS ICCWR ICCWAS ICCWD ICCWW ICCWE ICCWWS ICCWES ISB ISB1
S-VCC Operation Current
ICC1
ICC2 Input LOW Voltage Input HIGH Voltage Output LOW Voltage Output HIGH Voltage (CMOS) F-VCCW Lockout during Normal Operations F-VCCW during Block Erase, Bank Erase, Word Write or Lock-Bit Configuration Operations F-VCC Lockout Voltage VIL VIH VOL VOH1 VCCWLK VCCWH VLKO
8 0.6 VCC + 0.2 0.4
mA V V V V V V V 4 4 5
NOTES: 1. Reference values at VCC = 3.0 V and TA = +25C. 2. CMOS inputs are either VCC 0.2 V or GND 0.2 V. TTL inputs are either VIL or VIH. 3. Automatic Power Savings (APS) feature is placed automatically power save mode that addresses not switching more than 300 ns while read mode.
4. Includes F-RY/BY. 5. Block erases and word writes are inhibited when F-VCCW VCCWLK and not guaranteed in the range between VCCWLK (MAX.) and VCCWH (MIN.), and above VCCWH (MAX.).
10
Data Sheet
Stacked Chip (16M Flash & 4M SRAM)
LRS1331
FLASH MEMORY AC CHARACTERISTICS AC Test Conditions
PARAMETER Input pulse level Input rise and fall time Input and Output timing reference level Output load CONDITION 0 V to 2.7 V 10 ns 1.35 V 1TTL + CL (50 pF)
Read Cycle
TA = -25C to +85C, VCC = 2.7 V to 3.6 V PARAMETER Read Cycle Time Address to Output Delay F-CE to Output Delay* F-RP HIGH to Output Delay F-OE to Output Delay* F-CE to Output in LOW Z F-CE HIGH to Output in HIGH-Z F-OE to Output in LOW Z F-OE HIGH to Output in HIGH-Z Output Hold from Address, F-CE or F-OE change, whichever occurs first SYMBOL tAVAV tAVQV tELQV tPHQV tGLQV tELQX tEHQZ tGLQX tGHQZ tOH 0 0 15 0 40 MIN. 90 90 90 600 40 MAX. UNIT ns ns ns ns ns ns ns ns ns ns
NOTE: *F-OE may be delayed up to tELQV - tGLQV after the falling edge of F-OE without impact on tELQV.
Data Sheet
11
LRS1331
Stacked Chip (16M Flash & 4M SRAM)
Write Cycle (F-WE Controlled)1
TA = -25C to +85C, VCC = 2.7 V to 3.6 V PARAMETER Write Cycle Time F-RP HIGH Recovery to F-WE going to LOW F-CE Setup to F-WE going LOW F-WE Pulse Width F-WP VIH Setup to F-WE going HIGH F-VCCW Setup to F-WE going HIGH Address Setup to F-WE going HIGH Data Setup to F-WE going HIGH Data Hold from F-WE HIGH Address Hold from F-WE HIGH F-CE Hold from F-WE HIGH F-WE Pulse Width HIGH F-WE HIGH to F-RY/BY going LOW Write Recovery before Read F-VCCW Hold from Valid SRD, F-RY/BY HIGH Z F-WP VIH Hold from Valid SRD, F-RY/BY HIGH SYMBOL tAVAV tPHWL tELWL tWLWH tSHWH tVPWH tAVWH tDVWH tWHDX tWHAX tWHEH tWHWL tWHRL tWHGL tQVVL tQVSL 0 0 0 MIN. 90 1 10 50 100 100 50 50 0 0 10 30 100 MAX. UNIT ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2 2 NOTES
NOTES: 1. Read timing characteristics during block erase and word write operations are the same as during read-only operations. Refer to AC Characteristics for Read Cycle. 2. Refer to the `Flash Memory Command Definition' section for valid AIN and DIN for block erase or word write.
12
Data Sheet
Stacked Chip (16M Flash & 4M SRAM)
LRS1331
Write Cycle (F-CE Controlled)1
TA = -25C to +85C, VCC = 2.7 V to 3.6 V
PARAMETER Write Cycle Time F-RP HIGH Recovery to F-CE going to LOW F-WE Setup to F-CE going LOW F-CE Pulse Width F-WP VIH Setup to F-CE going HIGH F-VCCW Setup to F-CE going HIGH Address Setup to F-CE going HIGH Data Setup to F-CE going HIGH Data Hold from F-CE HIGH Address Hold from F-CE HIGH F-WE Hold from F-CE HIGH F-CE Pulse Width HIGH F-CE HIGH to F-RY/BY going LOW Write Recovery before Read F-VCCW Hold from Valid SRD, F-RY/BY HIGH Z F-WP VIH Hold from Valid SRD, F-RY/BY HIGH SYMBOL tAVAV tPHEL tWLEL tELEH tSHEH tVPEH tAVEH tDVEH tEHDX tEHAX tEHWH tEHEL tEHRL tEHGL tQVVL tQVSL 0 0 0 MIN. 90 1 0 60 100 100 50 50 0 0 0 20 100 MAX. UNIT ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2 2 NOTES
NOTES: 1. In system where F-CE defines the pulse width (within a F-WE timing waveform), all setup, hold, and inactive F-WE times should be measured relative to the F-CE waveform. 2. Refer to the `Flash Memory Command Definition' section for valid AIN and DIN for block erase or word write.
Block Erase and Word Write Performance
TA = -25C to +85C, VCC = 2.7 V to 3.6 V
SYMBOL PARAMETER Word Write Time 32K-word Block tWHQV1 tEHQV1 Word Write Time 4K-word Block Block Write Time 32K-word Block Block Write Time 4K-word Block tWHQV2 tEHQV2 tWHQV3 tEHQV3 tWHQV4 tEHQV4 tWHRZ1 tEHRZ1 tWHRZ2 tEHRZ2 Block Erase Time 32K-word Block Block Erase Time 4K-word Bock Full Chip Erase Time Set Lock-Bit Time Clear Block Lock-Bits Time Word Write Suspend Latency Time to Read Erase Suspend Latency Time to Read VCCW = 2.7 V to 3.6 V MIN. TYP.1 33 36 1.1 0.15 1.2 0.6 42 27.6 0.64 6.0 16.0 MAX.2 200 200 2.4 0.3 6 5 210 200 5 15 30 UNIT s s s s s s s s s s s NOTES 3 3 3 3 3 3 3 3 3
NOTES: 1. Reference values at TA = +25C and VCC = 3.0 V, VPP = 3.0 V. 2. Sampled, but not 100% tested. 3. Excludes system-level overhead.
Data Sheet
13
LRS1331
Stacked Chip (16M Flash & 4M SRAM)
FLASH MEMORY AC CHARACTERISTICS TIMING DIAGRAMS
Device Address Selection Address Stable tAVAV
Standby ADDRESS
Data Valid
F-CE tEHQZ
F-OE tGHQZ
F-WE
tGLQV tELQV tGLQX tELQX HIGH Z Valid Output tAVQV HIGH Z tOH
DQ
F-VCC tPHQV
F-RP
LRS1331-4
Figure 4. Read Cycle Timing Diagram
14
Data Sheet
Stacked Chip (16M Flash & 4M SRAM)
LRS1331
1
2
3
4
5
6
ADDRESS
AIN tAVAV
AIN tAVWH tWHAX
F-CE tELWL t WHEH tWHGL
F-OE tWHWL tEHQV1, 2, 3, 4
F-WE tWLWH tDVWH tWHDX HIGH-Z tPHWL Data Valid SRD tWHRL
DQ
DIN
DIN
DIN
F-RY/BY tSHWH tQVSL
F-WP
F-RP tVPWH VCCWH F-VCCW VCCWLK VIL NOTES: 1. VCC power-up and standby. 2. Write block erase or word write setup. 3. Write block erase confirm or valid address and data. 4. Automated erase or program delay. 5. Read status register data. 6. Write Read Array command. tQVVL
LRS1331-5
Figure 5. Write Cycle Timing Diagram (F-WE Controlled)
Data Sheet
15
LRS1331
Stacked Chip (16M Flash & 4M SRAM)
1
2
3
4
5
6
ADDRESS
AIN tAVAV
AIN tAVEH tEHAX
F-WE tWLEL tEHWH tEHGL
F-OE tEHEL tEHQV1, 2, 3, 4
F-CE tELEH tDVEH tEHDX HIGH-Z DQ tPHEL DIN DIN tEHRL Data Valid SRD DIN
F-RY/BY tSHEH tQVSL
F-WP
F-RP tVPEH VCCWH F-VCCW VCCWLK VIL NOTES: 1. VCC power-up and standby. 2. Write block erase or word write setup. 3. Write block erase confirm or valid address and data. 4. Automated erase or program delay. 5. Read status register data. 6. Write Read Array command. tQVVL
LRS1331-6
Figure 6. Write Cycle Timing Diagram (F-CE Controlled)
16
Data Sheet
Stacked Chip (16M Flash & 4M SRAM)
LRS1331
RESET OPERATIONS
TA = -25C to +85C, VCC = 2.7 V to 3.6 V PARAMETER F-RP Pulse LOW Time (if F-RP is tied to VCC, this specification is not applicable). F-RP LOW to Reset during Block Erase or Word Write F-VCC 2.7 V to F-RP HIGH SYMBOL tPLPH tPLRZ tVPH 100 MIN. 100 20 MAX. UNIT ns s ns 1, 2 3 NOTES
NOTES: 1. If F-RP is asserted while a block erase or word write operation is not executing, the reset will complete with 100 ns. 2. A reset time tPHQV is required from F-RY/BY going HIGH Z, or F-RP going HIGH until outputs are valid. 3. When the device power-up, holding F-RP LOW minimum 100 ns is required after VCC has been in predefined range and also has been stable there.
HIGH Z F-RY/BY (R) VOL VIH VIL tPLPH
F-RP (P)
A. Reset During Read Array Mode
HIGH Z F-RY/BY (R) VOL tPLRZ
F-RP (P)
VIH VIL tPLPH
B. Reset During Block Erase or Word Byte Write
2.7 V F-VCC VIL tVPH VIH VIL
F-RP (P)
C. F-RP Rising Timing
1331-7
Figure 7. AC Waveform for Reset Operation
Data Sheet
17
LRS1331
Stacked Chip (16M Flash & 4M SRAM)
SRAM AC ELECTRICAL CHARACTERISTICS AC Test Conditions
PARAMETER Input pulse level Input rise and fall time Input and Output timing reference level Output load*
NOTE: *Including scope and jig capacitance.
CONDITION 0.6 V to 2.2 V 5 ns 1.5 V 1TTL + CL (30 pF)
Read Cycle
TA = -25C to +85C, VCC = 2.7 V to 3.6 V PARAMETER
Read Cycle Time Address Access Time Chip Enable Access Time Output Enable to Output Valid Output hold from address change S-CE1, S-CE2 LOW to Output Active* S-OE LOW to Output Active* S-UB or S-LB LOW to Output in HIGH Impedance* S-CE1, S-CE2 HIGH to Output in HIGH Impedance* S-OE HIGH to Output in HIGH Impedance* S-UB or S-LB HIGH to Output Active* S-CE1 S-CE2 S-CE1 S-CE2 S-CE1 S-CE2
SYMBOL
tRC tAA tACE1 tACE2 tOE tOH tLZ1 tLZ2 tOLZ tBLZ tHZ1 HHZ2 tOHZ tBHZ
MIN.
85
MAX.
85 85 85 45
UNIT
ns ns ns ns ns ns ns ns ns ns
10 10 10 5 5 0 0 0 0 25 25 25 25
ns ns ns ns
NOTE: *Active output to HIGH impedance and HIGH impedance to output active tests specified for a 200 mV transition from steady state levels into the test load.
Write Cycle
TA = -25C to +85C, VCC = 2.7 V to 3.6 V PARAMETER
Write Cycle Time Chip Enable to End of Write Address Valid to End of Write Address Setup Time Write Pulse Width Write Recovery Time Input Data Setup Time Input Data Hold Time S-WE HIGH to Output Active* S-WE LOW to Output in HIGH Impedance*
SYMBOL
tWC tCW tAW tAS tWP tWR tDW tDH tOW tWZ
MIN.
85 70 70 0 60 0 35 0 5 0
MAX.
UNIT
ns ns ns ns ns ns ns ns ns
25
ns
NOTE: *Active output to HIGH impedance and HIGH impedance to output active tests specified for a 200 mV transition from steady state levels into the test load.
18
Data Sheet
Stacked Chip (16M Flash & 4M SRAM)
LRS1331
SRAM AC CHARACTERISTICS TIMING DIAGRAMS
tRC
ADDRESS tAA tACE
S-CE1 tLZ tHZ
S-CE2 tBE tHZ
S-UB, S-LB tBLZ tOE tBHZ
S-OE tOLZ tOHZ
DOUT
Data Valid tOH
NOTE: S-WE is HIGH for Read Cycle.
1331-8
Figure 8. Read Cycle Timing Diagram
Data Sheet
19
LRS1331
Stacked Chip (16M Flash & 4M SRAM)
tWC
ADDRESS tAW tCW
(NOTE 2)
S-CE1 tWR
S-CE2 tBW
(NOTE 3)
S-UB, S-LB tAS
(NOTE 4)
tWP
(NOTE 1)
tWR
(NOTE 5)
S-WE tWZ
(NOTE 7)
tOW
(NOTE 8)
DOUT tDW
(NOTE 6)
tDH
DIN NOTES: 1. A write occurs during the overlap of a LOW S-CE1, a HIGH S-CE2 and a LOW S-WE, A write begins at the latest transition among S-CE1 going LOW, S-CE2 going HIGH and S-WE going LOW. A write ends at the earliest transition among S-CE1 going HIGH, S-CE2 going LOW and S-WE going HIGH. tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the later of S-CE1 going LOW or S-CE2 going HIGH to the end of write. 3. tBW is measured from the time of going LOW S-UB or LOW S-LB to the end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as S-CE1 going HIGH, S-CE2 going LOW or S-WE going HIGH. 6. During this period, DQ pins are in the output state, therefore the input signals of opposite phase to the outputs must not be applied. 7. If S-CE1 goes LOW or S-CE2 goes HIGH simultaneously with S-WE going LOW or after S-WE going LOW, the outputs remain in HIGH impedance state. 8. If S-CE1 goes HIGH or S-CE2 goes LOW simultaneously with S-WE going HIGH or S-WE going HIGH, the outputs remain in HIGH impedance state.
Data Valid
1331-9
Figure 9. Write Cycle Timing Diagram (S-WE Controlled)
20
Data Sheet
Stacked Chip (16M Flash & 4M SRAM)
LRS1331
tWC
ADDRESS tAW tAS
(NOTE 4)
tCW
(NOTE 2)
tWR
S-CE1 tWR
(NOTE 5)
S-CE2 tBW
(NOTE 3)
S-UB, S-LB tWP
(NOTE 1)
S-WE
DOUT
HIGH IMPEDANCE tDW
(NOTE 6)
tDH
DIN
Data Valid
NOTES: 1. A write occurs during the overlap of a LOW S-CE1, a HIGH S-CE2 and a LOW S-WE, A write begins at the latest transition among S-CE1 going LOW, S-CE2 going HIGH and S-WE going LOW. A write ends at the earliest transition among S-CE1 going HIGH, S-CE2 going LOW and S-WE going HIGH. tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the later of S-CE1 going LOW or S-CE2 going HIGH to the end of write. 3. tBW is measured from the time of going LOW S-UB or LOW S-LB to the end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as S-CE1 going HIGH, S-CE2 going LOW or S-WE going HIGH. 6. During this period, DQ pins are in the output state, therefore the input signals of opposite phase to the outputs must not be applied.
1331-10
Figure 10. Write Cycle Timing Diagram (S-CE Controlled)
Data Sheet
21
LRS1331
Stacked Chip (16M Flash & 4M SRAM)
tWC
ADDRESS tAW
S-OE tCW
(NOTE 2)
S-CE1 tWR
(NOTE 5)
S-CE2 tAS
(NOTE 4)
tBW
(NOTE 3)
tWR
(NOTE 5)
S-UB, S-LB tWP
(NOTE 1)
S-WE HIGH IMPEDANCE tDW tDH
DOUT
DIN NOTES:
Data Valid
1. A write occurs during the overlap of a LOW S-CE1, a HIGH S-CE2 and a LOW S-WE, A write begins at the latest transition among S-CE1 going LOW, S-CE2 going HIGH and S-WE going LOW. A write ends at the earliest transition among S-CE1 going HIGH, S-CE2 going LOW and S-WE going HIGH. tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the later of S-CE1 going LOW or S-CE2 going HIGH to the end of write. 3. tBW is measured from the time of going LOW S-UB or LOW S-LB to the end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as S-CE1 going HIGH, S-CE2 going LOW or S-WE going HIGH.
1331-11
Figure 11. Write Cycle Timing Diagram (S-UB, S-LB Control)
22
Data Sheet
Stacked Chip (16M Flash & 4M SRAM)
LRS1331
SRAM DATA RETENTION CHARACTERISTICS
TA = -25C to +85C
PARAMETER Data Retention Supply Voltage Data Retention Supply Current Chip Enable Setup Time Chip Enable Hold Time SYMBOL VCCDR ICCDR tCDR tR CONDITIONS S-CE2 0.2 V or S-CE1 VCCDR - 0.2 V VCCDR = 1.2 V, S-CE2 0.2 V or S-CE1 VCCDR - 0.2 V 0 tRC MIN. 1 TYP.1 MAX. 3.6 5 UNIT V A ns ms NOTES 2 2
NOTES: 1. Reference value at TA = 25C, S-VCC = 3.0 V. 2. S-CE1 VCC - 0.2 V, S-CE2 VCC - 0.2 V (S-CE1 controlled) or S-CE2 0.2 V (S-CE2 controlled).
Data Retention Mode S-VCC 2.7 V tCDR tR
2.2 V VCCDR S-CE1 VCCDR - 0.2 V S-CE1 0V NOTE: To control the data retention mode at S-CE1, fix the input level of S-CE2 between VCCDR and VCCDR - 0.2 V, or 0 V and 0.2 V, and during the data retention mode.
1331-12
Figure 12. Data Retention Timing Diagram (S-CE1 Controlled)
Data Retention Mode S-VCC 2.7 V S-CE2 VCCDR tCDR tR
0.6 V S-CE2 0.2 V 0V
1331-13
Figure 13. Data Retention Timing Diagram (S-CE2 Controlled)
Data Sheet
23
LRS1331
Stacked Chip (16M Flash & 4M SRAM)
GENERAL DESIGN GUIDELINES Supply Power
Maximum difference (between F-VCC and S-VCC) of the voltage is less than 0.3 V.
Data Protection Through F-VCCW
When the level of F-VCCW is lower than F-VCCWK (lockout voltage), write operation on the flash memory is disabled. All blocks are locked and the data in the blocks are completely write protected. For the lockout voltage refer to the `DC Characteristics' section.
Power Supply and Chip Enable of Flash Memory and SRAM
S-CE1 should not be LOW and S-CE2 should not be HIGH when F-CE is LOW simultaneously. If the two memories are active together, they may not operate normally because of interference noises or data collision on DQ bus. Both F-VCC and S-VCC need to be applied by the recommended supply voltage at the same time except SRAM data retention mode.
Data Protection During Voltage Transition
DATA PROTECTION THROUGH F-RP When the F-RP is kept LOW during power up and power down sequence, write operation on the flash memory is disabled, write protecting all blocks. For details of F-RP control refer to the `Flash Memory AC Electrical Characteristics' section.
Power Up Sequence
When turning on Flash memory power supply, keep F-RP LOW. After F-VCC reaches over 2.7 V, keep F-RP LOW for more than 100 ns.
DESIGN CONSIDERATIONS Power Supply Decoupling
To avoid a bad effect on the system by flash memory power switching characteristics, each device should have a 0.1 F ceramic capacitor connected between its VCC and GND and between its VCCW and GND. LOW inductance capacitors should be placed as close as possible to package leads.
Device Decoupling
The power supply needs to be designed carefully because one of the SRAM and the Flash Memory is in standby mode when the other is active. A careful decoupling of power supplies is necessary between SRAM and Flash Memory. Note peak current caused by transition of control signals (F-CE, S-CE1, S-CE2).
VCCW Trace on Printed Circuit Boards
Updating the memory contents of flash memories that reside in the target system requires that the printed circuit board designer pay attention to the VCCW Power Supply trace. Use similar trace widths and layout considerations given to the VCC power bus.
FLASH MEMORY DATA PROTECTION
Noises having a level exceeding the limit specified in the specification may be generated under specific operating conditions on some systems. Such noises, when induced onto F-WE signal or power supply may be interpreted as false commands, causing undesired memory updating. To protect the data store in the flash memory against unwanted overwriting, systems operating with the flash memory should have the following write protect designs, as appropriate:
The Inhibition of Overwrite Operation
Please do not execute reprogramming `0' for the bit which has already been programmed `0'. Overwrite operation may generate unerasable bit. In case of reprogramming `0' to the data which has been programmed `1'. * Program `0' for the bit in which you want to change data from `1' to `0'. * Program `1' for the bit which has already been programmed `0'. For example, changing data from `1011110110111101' to `1010110110111100' requires `1110111111111110' programming.
Protecting Data in Specific Block
By setting a F-WP to LOW, only the boot block can be protected against overwriting. Parameter and main blocks with F-WP cannot be locked. System program, etc., can be locked by storing them in the book block. For further information on setting/resetting of block bit, and controlling of F-WP and F-RP, refer to the specification, see the Command Definitions section.
Power Supply
Block erase, full chip erase, word write and lock-bit configuration with an invalid VCCW (see `DC Characteristics') produce spurious results and should not be attempted. Device operations at invalid VCC voltage product spurious results and should not be attempted.
24
Data Sheet
Stacked Chip (16M Flash & 4M SRAM)
LRS1331
OUTLINE DIMENSIONS
FBGA072-P-0811
B
A INDEX
TOP VIEW 8.0 +0.2 -0 11.0 +0.2 -0 0.10 SIDE VIEW S S
(See Detail) 0.10 S
0.40 TYP.
DETAIL
1.1 TYP. 0.8 TYP. 0.4 TYP. C 1.4 MAX. 0.35 0.05 1.2 TYP. H BOTTOM VIEW G D F E D C B A 1 2 3 45 6 7 8 9 10 11 12 0.8 TYP. 0.4 TYP.
0.45 0.05
0.30 M 0.15 M
S AB S CD
72FBGA
NOTE: Dimensions are in mm.
Data Sheet
25
Stacked Chip (16M Flash & 4M SRAM)
LRS1331
LIFE SUPPORT POLICY
SHARP components should not be used in medical devices with life support functions or in safety equipment (or similiar applications where component failure would result in loss of life or physical harm) without the written approval of an officer of the SHARP Corporation.
LIMITED WARRANTY
SHARP warrants to its Customer that the Products will be free from defects in material and workmanship under normal use and service for a period of one year from the date of invoice. Customer's exclusive remedy for breach of this warranty is that SHARP will either (i) repair or replace, at its option, any Product which fails during the warranty period because of such defect (if Customer promptly reported the failure to SHARP in writing) or, (ii) if SHARP is unable to repair or replace, refund the purchase price of the Product upon its return to SHARP. This warranty does not apply to any Product which has been subjected to misuse, abnormal service or handling, or which has been altered or modified in design or construction, or which has been serviced or repaired by anyone other than Sharp. The warranties set forth herein are in lieu of, and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will Sharp be liable, or in any way responsible, for any incidental or consequential economic or property damage. The above warranty is also extended to Customers of Sharp authorized distributors with the following exception: reports of failures of Products during the warranty period and return of Products that were purchased from an authorized distributor must be made through the distributor. In case Sharp is unable to repair or replace such Products, refunds will be issued to the distributor in the amount of distributor cost. SHARP reserves the right to make changes in specifications at any time and without notice. SHARP does not assume any responsibility for the use of any circuitry described; no circuit patent licenses are implied.
NORTH AMERICA
EUROPE
ASIA
SHARP Microelectronics of the Americas 5700 NW Pacific Rim Blvd. Camas, WA 98607, U.S.A. Phone: (360) 834-2500 Telex: 49608472 (SHARPCAM) Facsimile: (360) 834-8903 http://www.sharpsma.com
(c)1999 by SHARP Corporation
SHARP Electronics (Europe) GmbH Microelectronics Division Sonninstrae 3 20097 Hamburg, Germany Phone: (49) 40 2376-2286 Facsimile: (49) 40 2376-2232 http://www.sharpmed.com
SHARP Corporation Integrated Circuits Group 2613-1 Ichinomoto-Cho Tenri-City, Nara, 632, Japan Phone: +81-743-65-1321 Facsimile: +81-743-65-1532 http://www.sharp.co.jp
Reference Code SMA99087

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